PIC16C62B-20/SS【PDF 3/120 页】IC MCU OTP 2KX14 PWM 28SSOP

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PIC16C62B/72A

DS35008B-page 100

Preliminary

1998 Microchip Technology Inc.

FIGURE 13-16: I2C BUS DATA TIMING

TABLE 13-12: I2C BUS DATA REQUIREMENTS

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

100*

THIGH

Clock high time

100 kHz mode

4.0

—

Device must operate at a min-

imum of 1.5 MHz

400 kHz mode

0.6

—

Device must operate at a min-

imum of 10 MHz

SSP Module

1.5TCY

—

101*

TLOW

Clock low time

100 kHz mode

4.7

—

Device must operate at a min-

imum of 1.5 MHz

400 kHz mode

1.3

—

Device must operate at a min-

imum of 10 MHz

SSP Module

1.5TCY

—

102*

SDA and SCL rise

time

100 kHz mode

—

1000

400 kHz mode

20 + 0.1Cb

300

Cb is specified to be from

10-400 pF

103*

SDA and SCL fall

time

100 kHz mode

—

300

400 kHz mode

20 + 0.1Cb

300

Cb is specified to be from

10-400 pF

90*

TSU:STA

START condition

setup time

100 kHz mode

4.7

—

Only relevant for repeated

START condition

400 kHz mode

0.6

—

91*

THD:STA

START condition hold

time

100 kHz mode

4.0

—

After this period the first clock

pulse is generated

400 kHz mode

0.6

—

106*

THD:DAT

Data input hold time

100 kHz mode

—

400 kHz mode

0.9

107*

TSU:DAT

Data input setup time

100 kHz mode

250

—

Note 2

400 kHz mode

100

—

92*

TSU:STO

STOP condition setup

time

100 kHz mode

4.7

—

400 kHz mode

0.6

—

109*

TAA

Output valid from

clock

100 kHz mode

—

3500

Note 1

400 kHz mode

—

110*

TBUF

Bus free time

100 kHz mode

4.7

—

Time the bus must be free

before a new transmission

can start

400 kHz mode

1.3

—

Bus capacitive loading

—

400

These parameters are characterized but not tested.

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall-

ing edge of SCL to avoid unintended generation of START or STOP conditions.

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT

≥

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR

max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.

Note:

Refer to Figure 13-4 for load conditions.

100

101

103

106

107

109

110

102

SCL

SDA

Out

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